Step 4 · Placement

Session & state check (before touching anything)

1. One step per session: if this session already did substantive work for another step, stop and ask for a fresh session.
2. Read docs/flow-state.md (canonical header line; foreign file → stop and ask). Confirm step 3 is done; read the schematic/netlist deliverables, BOM, docs/pinmap.md. Not satisfied → stop and report.
3. This step already done with no issue targeting it → re-run: ask intent first. Already in-progress → aborted or concurrent session: ask before proceeding. Marked rework → redo what the rework note requires, then wrap up.
4. Issues-table entries with target step = 4 → fix mode.
5. Set step 4 in-progress. Rebuild context from disk only.

Execute

Adopt-and-audit path: an inherited placement recorded in flow-state (inherited: <path>, same-EDA only) is ingested, then audited by this step's own checks — the structure gate below still runs (the enclosure decision is the user's even when the placement is theirs), and the four self-checks must pass at zero. The bar doesn't move; only the labor does.

⛔ Hard gate (before any placement work; the AI must not wave itself through)

Board outline, component side, and orientation are enclosure-level decisions — the user's, not your defaults.

1. Pull real mechanical data from the key components' official specs (outlines, clearances, connector exit positions)
2. Distill the concrete structural conflicts (e.g. what doesn't fit in which clearance, who competes for which board edge, what large mechanical parts — battery, display, shield, heatsink — cover)
3. Cross-check the structure decisions against docs/fab-profile.md — layer count, stackup, and clearances must be achievable in the frozen profile; changing the profile is a plan amendment, never a silent swap
4. Have the user decide via multiple-choice with a recommended option; only then generate coordinates

The structure gate is re-entrant: if packing later proves the confirmed decisions infeasible — or shows the layer count itself must change — come back to the user with the evidence and re-decide before continuing (and amend the dev-plan if the stackup/power-plane strategy changes). Never force a fit past a decision the evidence has invalidated.

Placement

• Zoning: power flow + short signal paths + clearance rules (e.g. antenna/sensor keep-outs per datasheet, connectors at board edges, high-frequency loops tight)
• Switching regulators: check the inductor orientation first — if the output side is a plane net, orientation is a free variable; never let the SW node detour
• Generate offline + self-check, then push once: explicit coordinates for anchors + grid packing per zone; run the four global self-checks (overlap / out-of-bounds / clearance / keep-out) to zero conflicts before pushing to the EDA. Decouple placement correctness from tool operation.
• The push is an EDA mutation like any other — same API/bridge discipline as routing: after a timeout the EDA-side script may still be running (poll for completion, never re-send); batch pushes must be idempotent; reconcile a partial apply before retrying.

Done criteria: four self-checks at zero conflicts + floorplan presented and confirmed by the user.

Fix mode (entries with target step = 4)

Fix only the listed issues; after moving any part, re-run all four self-checks. Append to docs/rework-log-N.md (symptom / root cause / fix; N = last verification round + 1) → set the issue fixed-pending-verify, citing the rework-log entry in the same edit. Then assess cascading rework before routing: placement changes usually invalidate routing — if so, set step 5 to rework with a one-line reason in its steps-table row. Route last: step 5 first (if rework), then step6-verify, each in a fresh session.

Wrap up

Mark step 4 done, tell the user: new session, run step5-routing (Claude Code: /boardless-pcb:step5-routing).