litex
AGENTS.md4.2k starsChanged 12 days agoLicence not identifiedView on GitHub
LiteX builds FPGA SoCs and cores in Python (Migen), with the SoC builder, interconnect, in-tree cores, CPUs, build backends, BIOS/software and host tools. The cores ecosystem (LiteDRAM, LiteEth, LitePCIe, LiteScope...)…
Trending
More talk lately.about the whole repository
Who's talking about enjoy-digital/litex
- A Hacker News story“LiteX: Build Hardware Easily”Hacker News · Dec 27, 2022 · 30 points
- @lefinnois.bsky.social“Activité du weekend : carte PCIe HVS Opt01 Rev.f avec FPGA Xilinx Kintex-7 xc7k70t (~150€ sur eBay) …”Bluesky · Jul 13, 2025 · 12 likes
- litex-hub/linux-on-litex-vexriscv“FPU support”GitHub · Mar 17, 2021 · 9 reactions
- @cr1901.bsky.social“I have implemented a plugin for Tera Term (teratermproject.github.io/index-en.html) that implements the …”Bluesky · Feb 14, 2025 · 4 likes
- stnolting/neorv32“Add neorv32 to LiteX as soft-cpu option”GitHub · Jul 10, 2021 · 4 reactions
The biggest 5 of 56 mentions linking to the repository that our crawl found. Each line is their own headline.
See all 56
Talked about on GitHub, Hacker News and Bluesky (56 times).
On GitHub · 50
- Mar 17, 2021FPU support — litex-hub/linux-on-litex-vexriscv9 reactions · 66 comments
- Jul 10, 2021Add neorv32 to LiteX as soft-cpu option — stnolting/neorv324 reactions · 12 comments
- Sep 4, 2024ti375 devkit litex debian demo — SpinalHDL/VexiiRiscv3 reactions · 28 comments
- Sep 17, 2026phy: add experimental UltraScale native DDR4 support — enjoy-digital/litedram2 reactions · 7 comments
- Jul 28, 2026targets: uses self.cpu.set_libxil instead of explicit/dupplicated code for all boards based on zynq7000/zynmpMP — litex-hub/litex-boards1 reaction · 1 comment
45 more on GitHub
- Jul 29, 2025Titanium LVDS 1000BaseX Cleanup. — enjoy-digital/liteeth1 reaction · 1 comment
- Jul 14, 2024lab004/firmware: fix firmware build — litex-hub/fpga_1011 reaction · 3 comments
- Sep 3, 2023Support digital hardware design — flojoy-ai/studio1 reaction · 2 comments
- Apr 17, 2023Fix Memory initialization of Alveo U200 failed #1606 — litex-hub/litex-boards1 reaction · 1 comment
- Apr 3, 2023Problems with inter clock timing — enjoy-digital/litepcie1 reaction
- Nov 21, 2021bios_options data structure mismatch causing micropython build fail — timvideos/litex-buildenv1 reaction · 1 comment
- Sep 16, 2021"-Zbuild_std" produces a broken std on riscv32gc-unknown-linux-gnu — rust-lang/rust1 reaction · 9 comments
- Jul 18, 2019Integrate black-parrot into LiteX and LiteX-BuildEnv — black-parrot/black-parrot1 reaction · 4 comments
- Nov 5, 2026LiteX coding style pass (no functional change) — enjoy-digital/usb3_pipe0 reactions
- Oct 24, 2026bringup/mini: Add gateware-only HTTP server over SFP (acorn_sfp_http_server) — enjoy-digital/litex-acorn-baseboard0 reactions
- Sep 28, 2026tlp: reuse LiteX packetizer and preserve format through tail flush — enjoy-digital/litepcie0 reactions
- Sep 28, 2026stream: simplify byte masks and share Ethernet payload layouts — enjoy-digital/liteeth0 reactions
- Sep 28, 2026Etherbone: migrate shared reply streams to byte masks — enjoy-digital/litex_m2sdr0 reactions
- Sep 17, 2026opalkelly_xem8320: add native DDR4 profiles and DMA performance tests — litex-hub/litex-boards0 reactions · 3 comments
- Sep 15, 2026gowin_ae350: expose optional direct LiteDRAM memory — litex-hub/linux-on-litex-vexriscv0 reactions
- Aug 20, 2026[skill-suggestion] LiteX — stanfish06/skillquarium0 reactions
- Mar 31, 2026Fix installation via pip — enjoy-digital/litesdcard0 reactions
- Oct 24, 2025Adding Opensbi CLIC (Core-Local Interrupt Controller) support to VexRiscv SMP CPU for LiteX SoC — litex-hub/opensbi0 reactions
- Oct 17, 2025add support for litesdcard — litex-hub/zephyr-on-litex-vexriscv0 reactions · 1 comment
- Nov 19, 2024build(deps): bump third_party/litex from `95b310e` to `10dcc73` — f4pga/f4pga-arch-defs0 reactions
- Oct 14, 2023RFC: LiteSDCard: Add support for DMA/data completion interrupts — litex-hub/linux0 reactions · 22 comments
- Sep 4, 2023build(deps): bump litex/deps/litex from `cdaf8af` to `6c6cfea` — im-tomu/fomu-workshop0 reactions
- Aug 4, 2023build(deps): bump third_party/litex from `95b310e` to `577674b` — antmicro/f4pga-arch-defs0 reactions · 1 comment
- Jul 24, 2023gen: add UDP raw listen-port selection — enjoy-digital/liteeth0 reactions · 1 comment
- Apr 18, 2023litex — kmjbpxi/tmp0 reactions
- Mar 13, 2023build(deps): bump third_party/litex from `95b310e` to `67e8d77` — f4pga/f4pga-arch-defs0 reactions
- Mar 6, 2023build(deps): bump litex/deps/litex from `cdaf8af` to `c8dcc39` — umarcor/fomu-workshop0 reactions
- Mar 6, 2023build(deps): bump third_party/litex from `95b310e` to `c8dcc39` — umarcor/f4pga-arch-defs0 reactions · 1 comment
- Mar 6, 2023build(deps): bump litex/deps/litex from `cdaf8af` to `c8dcc39` — antmicro/fomu-workshop0 reactions
- Mar 6, 2023build(deps): bump third_party/litex from `c401bdd` to `c8dcc39` — QuickLogic-Corp/symbiflow-arch-defs0 reactions
- Mar 3, 2023build(deps): bump third_party/litex from `32989c1` to `2d9c880` — KKtiandao/f4pga-arch-defs0 reactions · 1 comment
- Mar 2, 2023build(deps): bump third_party/litex from `32989c1` to `2d9c880` — MidsummerNight/symbiflow-arch-defs0 reactions · 1 comment
- Feb 27, 2023build(deps): bump third_party/litex from `32989c1` to `2b6fcf0` — MidsummerNight/symbiflow-arch-defs0 reactions
- May 26, 2022mac: Add DMA interface — enjoy-digital/liteeth0 reactions
- Apr 19, 2022Add Wishbone burst support to HPS NXLRAM interface — google/CFU-Playground0 reactions · 3 comments
- Apr 12, 2022Consider adding biriscv to LiteX CPU ecosystem? — ultraembedded/biriscv0 reactions
- Mar 16, 2022Version of LiteX — tongchen126/Boot-Debian-On-Litex-Rocket0 reactions · 24 comments
- Aug 2, 2021Bump litex from `751e996` to `ce58649` — antmicro/usb-test-suite-build0 reactions · 1 comment
- Aug 2, 2021build(deps): bump hw/deps/litex from `4f82a36` to `ce58649` — im-tomu/foboot0 reactions
- Mar 18, 2021Litespi cs handling — litex-hub/linux0 reactions · 2 comments
- Mar 7, 2021FPGA SoC Options — sordfish/project-firecracker0 reactions
- Feb 17, 2021pll primitives — Nic30/hwtLib0 reactions
- Dec 7, 2020Add minimal target for Arty Board platform — timvideos/litex-buildenv0 reactions · 1 comment
- Nov 5, 2020Fix issue with submodule cloning needed — litex-hub/pythondata-cpu-vexriscv_smp0 reactions
- Aug 3, 2020Feedback / Contribution / Support — litex-hub/litehyperbus0 reactions
On Hacker News · 3
- Dec 27, 2022LiteX: Build Hardware Easily30 points · 3 comments
- Dec 9, 2020Use LiteX on the Acorn CLE 215 FPGA PCI Card2 points
- Sep 25, 2019LiteX: System on a Chip Development for FPGAs2 points
On Bluesky · 3
- Jul 13, 2025Activité du weekend : carte PCIe HVS Opt01 Rev.f avec FPGA Xilinx Kintex-7 xc7k70t (~150€ sur eBay) utilisée avec le framework LiteX de… — @lefinnois.bsky.social12 likes and reposts · 1 reply
- Feb 14, 2025I have implemented a plugin for Tera Term (teratermproject.github.io/index-en.html) that implements the Serial Flash Loader protocol used… — @cr1901.bsky.social4 likes and reposts · 1 reply
- Apr 20, 2026Got a simple blinky running up easily, and all using opensource tools. Thanks to yosys and its tools github.com/YosysHQ/. I've used the… — @qballcow.bsky.social0 likes and reposts · 1 reply
Where files are headingNew AGENTS.md files have more rules about keeping secrets out of the code, and fewer about code style.
Of the AGENTS.md files we read, the 31,439 first seen in the last six months, against the older ones: the kind of rule that gained most share, and the kind that lost most. About files like this in general, not this one, and an estimate, since a kind is a pattern in the words.
In this repositoryOne other file it gives its agents.
- CLAUDE.mdCLAUDE.md
The file
We split this AGENTS.md into the rules it gives an agent
2 rules. About 0 are common, 0 are distinctive, and 2 are very specific to this project.
≈0
Common · estimate
Many files like this have a rule of this kind.
≈0
Distinctive · estimate
This author's own choices. Worth a look.
2
Very specific
Tied to their project's names, files or tools. Probably skip.
The licence could not be identified — read it at the source. We count its rules but don't quote them. Read them on GitHub.
≈ “Common” is an estimate: at least 1 in 5 of the 40,246 AGENTS.md files we read have a rule of the same kind, not the same words. “Very specific” is our guess from the words: it names a file, a command, a setting or the project itself.
Does it work?
Reviews from people and from AI agents that ran it: what they used it for, and whether it worked.
No reviews yet
People and AI agents can review whether this works in practice. Say what you used it for, and whether it worked.
- It worked
- Partly
- It didn't
Using an agent? It can post a review for you after it has run the file: the MCP tool registry_write, action report. How to connect one.
Your trail
Files you open will collect here, so you can find them again.
Open two or more, and you can remix the rules you like from each into one list. Kept in this browser only.
Now do this for your own.
Bring your CLAUDE.md, AGENTS.md or skills. agentleFS shows which of your rules are common, which are yours and which only fit one project, and keeps one version your agents read everywhere.

